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In relation to a work-around for a tool issue, it is required to 'cheat' synthesis and optimization to keep an unused signal, but the synthesis appears to be pretty 'smart' at detecting and removing actually unused signals. For example, the code below is optimized away, since the
unused_*
signal are not used elsewhere:Usually there is tool support for attributes like 'keep', but that does not work with the tool version. Having an unused chip output is neither desirable.
So, is there some general way to 'cheat' synthesis and optimization to not optimized a signal away, even through the signal is effectively unused?
EquipDev
EquipDevEquipDev
2 Answers
Make the signal an output.You may need to connect it all way to the top level output (pin) in a hierarchical design.
jamihashjamihash
Found a way to generate an internal constant '1' value after 2 cycles (
one
in code below), and this constant '1' value can then be ORed on the unused signal (one or unused_1
), and the resulting value can then be ANDed on some other expression without effect since constant '1' (used_1 and (one or unused_1)
). The used_as_1
when then experience an additional delay, but with same logical value.A way to generate and internal constant '1' for both Altera, Lattice, and Xilinx is:
The current versions of these tools do not identify this as being a constant 1, thus do not remove the circuit.
EquipDevEquipDev